A conventional image processing apparatus calculates a pixel value of converted image by referring to pixel values of unconverted image stored in a main memory. The image processing apparatus includes a cache memory in which pixel values of unconverted image can be stored in order to decrease the number of times of access to the main memory. When calculating the pixel value of converted image, first the image processing apparatus confirms whether the pixel values of the unconverted image is stored in the cache memory. When the pixel values of the unconverted image is stored, the image processing apparatus calculates the pixel values of the converted image by referring to the pixel values of the unconverted image stored in the cache memory. On the other hand, when the pixel values of unconverted image is not stored, the image processing apparatus transfers the pixel values of unconverted image necessary for the calculation of the pixel value of converted image from the main memory to the cache memory.
When the cache memory is composed of a single-port Static Random Access Memory (SRAM), because plural pixel values of unconverted image are stored in different cache lines, it is necessary to obtain cache access plural times to read out all the pixel values of unconverted image necessary for the calculation of the pixel value of converted image. As a result, processing efficiency of the image processing apparatus is degraded.
On the other hand, all the pixel values of unconverted image necessary for the calculation of the pixel value of converted image can be read out by the one-time cache access even if the plural pixel values of unconverted image are stored in the different cache lines, thereby improving the processing efficiency of the image processing apparatus.
For example, when the cache memory is composed of a multi-port SRAM that has ports corresponding to the number of pixel values of unconverted image to be referred to, all the pixel values of unconverted image can be read out by the one-time cache access. However, because a read rate of the multi-port SRAM is slower than that of the single-port SRAM, an operating frequency of a circuit constituting the image processing apparatus is lowered to degrade the processing efficiency of the image processing apparatus. Moreover, when the number of pixel values of unconverted image to be referred to is increased (for example, at least three pixel values of unconverted image), it is necessary to provide the ports corresponding to the number of pixel values of unconverted image. Because generally cost of the SRAM is increased according to the number of ports, the use of the SRAM having the ports corresponding to the number of pixel values of unconverted image also increases cost of the image processing apparatus.
That is, the processing efficiency of the image processing apparatus is degraded when the cache memory is composed of the single-port SRAM. The cost of the image processing apparatus is increased when the cache memory is composed of the multi-port SRAM.